![]() ![]() Design Automation of Electronic Systems, vol. Hayes, “Probabilistic transfer matrices in symbolic reliability analysis of logic circuits,” ACM Trans. Hayes, “Tracking uncertainty with probabilistic logic circuit testing,” IEEE Design and Test of Computers, vol. of Design Automation and Test in Europe (DATE 2005), Munich, Germany, pp. ![]() Hayes, “Accurate reliability evaluation and enhancement via probabilistic transfer matrices,” in Proc. Workshop on Logic and Synthesis (IWLS), pp. Hayes, “Evaluating circuit reliability under probabilistic gate-level fault models,” in Int. on Computer Aided Design (ICCAD’03), San Jose, CA, pp. Mundy, “A probabilistic-based design methodology for nanoscale computation,” in Proc. McCluskey, “Probabilistic treatment of general combinational networks,” IEEE Trans. Borkar, “Designing reliable systems from unreliable components: the challenge of transistor variability and degradation,” IEEE Micro., vol. Reitsma, “Chip-level soft error estimation method,” IEEE Device and Materials Reliability, vol. Based on the simulation results, the proposed approach exhibits the computational complexity of. Also, the proposed approach benefits from scalable runtime and memory requirements. Also, the proposed approach introduces a probability distribution function model to propagate the waveform of errors in the circuit to consider all masking mechanisms. The proposed approach is based on nonlinear probabilistic graphs to find the probability of error for each gate after passing the circuit for an infinite number of clock cycles. ![]() This paper proposes a fast and scalable approach using probabilistic signal flow graphs to analyze the reliability of sequential logic circuits in the presence of multiple event transients. Moreover, it is essential to consider the waveform of errors in sequential circuits into account, which makes it more complex. This figure becomes even more complicated in sequential circuits due to the feedback loops, where errors may store in flip-flops and re-enter the circuit. However, the reliability analysis of logic circuits is high computational complexity, because of multiple simultaneous errors, propagating the errors, masking mechanisms, re-convergent paths, etc. Vahid Hamiyati Vaghef, Ali Peiravi AbstractĪs the transistor sizes shrunk in advanced VLSI circuits recently, their susceptibility to the transient faults significantly has been increased which makes the reliability analysis of logic circuits more important. ![]()
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